Altera cyclone V Technical Reference page 2077

17-862
AXI_Bus_Mode
Module Instance
emac0
emac1
Offset:
0x1028
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
en_lpi lpi_
xit_
RW 0x0
frm
RW
0x0
15 14
Reserved onekb
AXI_Bus_Mode Fields
Bit
31
en_lpi
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software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
axi_
be aal
RW RO
0x0 0x0
Name
When set to 1, this bit enables the LPI mode
supported by the AXI master and accepts the LPI
request from the AXI System Clock controller. When
set to 0, this bit disables the LPI mode and always
denies the LPI request from the AXI System Clock
controller.
0x0
0x1
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
wr_osr_lmt
9 8 7 6
Reserved
Description
Value Description
Disable LPI Mode
Enable LPI Mode
0xFF701028
0xFF703028
21 20 19
RW 0x1
5 4 3
blen1 blen8
6
RW
0x0
Ethernet Media Access Controller
cv_5v4
2016.10.28
Register Address
18 17 16
rd_osr_lmt
RW 0x1
2 1 0
blen4 undefine
d
RW RW
0x0 0x0 RO 0x1
Access Reset
RW 0x0
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