Altera cyclone V Technical Reference page 2080

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
AHB_or_AXI_Status Fields
Bit
1
axirdsts
0
axwhsts
Current_Host_Transmit_Descriptor
The Current Host Transmit Descriptor register points to the start address of the current Transmit
Descriptor read by the DMA.
Module Instance
emac0
emac1
Offset:
0x1048
Access:
RO
31 30
15 14
Ethernet Media Access Controller
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
When high, it indicates that AXI Master's read
channel is active and transferring data.
When high, it indicates that AXI Master's write
channel is active and transferring data
0xFF700000
0xFF702000
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
Bit Fields
25 24 23 22
curtdesaptr
RO 0x0
9 8 7 6
curtdesaptr
RO 0x0
Current_Host_Transmit_Descriptor
21 20 19 18
5 4 3 2
Access
Register Address
0xFF701048
0xFF703048
21 20 19 18
5 4 3 2
17-865
17 16
1 0
axird axwhsts
sts
RO 0x0
RO
0x0
Reset
RO 0x0
RO 0x0
17 16
1 0
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