Altera cyclone V Technical Reference page 2072

cv_5v4
2016.10.28
Bit
14
ere
13
fbe
10
ete
9
rwe
Ethernet Media Access Controller
Send Feedback
Name
When this bit is set with Normal Interrupt Summary
Enable (Bit 16), the Early Receive Interrupt is enabled.
When this bit is reset, the Early Receive Interrupt is
disabled.
Value
0x0
0x1
When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Fatal Bus Error
Interrupt is enabled. When this bit is reset, the Fatal
Bus Error Enable Interrupt is disabled.
Value
0x0
0x1
When this bit is set with an Abnormal Interrupt
Summary Enable (Bit 15), the Early Transmit
Interrupt is enabled. When this bit is reset, the Early
Transmit Interrupt is disabled.
Value
0x0
0x1
When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Receive Watchdog
Timeout Interrupt is enabled. When this bit is reset,
the Receive Watchdog Timeout Interrupt is disabled.
Value
0x0
0x1
Description
Description
Early Receive Interrupt Disabled
Early Receive Interrupt Enabled
Description
Fatal Bus Error Interrupt Disabled
Fatal Bus Error Interrupt Enabled
Description
Early Transmit Interrupt Disabled
Early Transmit Interrupt Enabled
Description
Receive Watchdog Timeout Interrupt
Disabled
Receive Watchdog Timeout Interrupt
Enabled
17-857
Interrupt_Enable
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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