Altera cyclone V Technical Reference page 2079

17-864
AHB_or_AXI_Status
Bit
2
blen8
1
blen4
0
undefined
AHB_or_AXI_Status
This register provides the active status of the AXI interface's read and write channels. This register is useful
for debugging purposes.
Module Instance
emac0
emac1
Offset:
0x102C
Access:
RO
Altera Corporation
Name
When this bit is set to 1, the GMAC-AXI is allowed to
select a burst length of 8 on the AXI Master interface.
Setting this bit has no effect when UNDEFINED is set
to 1.
Value
0x0
0x1
When this bit is set to 1, the GMAC-AXI is allowed to
select a burst length of 4 on the AXI Master interface.
Setting this bit has no effect when UNDEFINED is set
to 1.
Value
0x0
0x1
This bit is read-only bit and indicates the complement
(invert) value of Bit 16 (FB) in Register 0 (Bus Mode
Register[16]). * When this bit is set to 1, the GMAC-
AXI is allowed to perform any burst length equal to
or below the maximum allowed burst length
programmed in Bits[7:1]. * When this bit is set to 0,
the GMAC-AXI is allowed to perform only fixed
burst lengths as indicated by BLEN16, BLEN8, or
BLEN4, or a burst length of 1.
Value
0x0
0x1
0xFF700000
0xFF702000
Description
Description
AXI No Fixed Busrts
AXI Fixed Burst BLEN = 8
Description
AXI No Fixed Busrts
AXI Fixed Burst BLEN = 4
Description
Fixed Burst Lengths 4 to 16
Any Burst Length up to max
Base Address
2016.10.28
Access Reset
RW 0x0
RW 0x0
RO 0x1
Register Address
0xFF70102C
0xFF70302C
Ethernet Media Access Controller
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