Altera cyclone V Technical Reference page 2074

cv_5v4
2016.10.28
Bit
3
tje
2
tue
1
tse
0
tie
Missed_Frame_And_Buffer_Overflow_Counter
The DMA maintains two counters to track the number of frames missed during reception. This register
reports the current value of the counter. The counter is used for diagnostic purposes. Bits[15:0] indicate
missed frames because of the host buffer being unavailable. Bits[27:17] indicate missed frames because of
Ethernet Media Access Controller
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Name
When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Transmit Jabber
Timeout Interrupt is enabled. When this bit is reset,
the Transmit Jabber Timeout Interrupt is disabled.
Value
0x0
0x1
When this bit is set with Normal Interrupt Summary
Enable (Bit 16), the Transmit Buffer Unavailable
Interrupt is enabled. When this bit is reset, the
Transmit Buffer Unavailable Interrupt is disabled.
Value
0x0
0x1
When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Transmission Stopped
Interrupt is enabled. When this bit is reset, the
Transmission Stopped Interrupt is disabled.
Value
0x0
0x1
When this bit is set with Normal Interrupt Summary
Enable (Bit 16), the Transmit Interrupt is enabled.
When this bit is reset, the Transmit Interrupt is
disabled.
Value
0x0
0x1
Missed_Frame_And_Buffer_Overflow_Counter
Description
Description
Transmit Jabber Timeout Interrupt Disabled
Transmit Jabber Timeout Interrupt Enabled
Description
Transmit Buffer Unavailable Interrupt
Disabled
Transmit Buffer Unavailable Interrupt
Enabled
Description
Transmit Stopped Interrupt Disabled
Transmit Stopped Interrupt Enabled
Description
Transmit Interrupt Disabled
Transmit Interrupt Enabled
17-859
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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