Altera cyclone V Technical Reference page 2081

Hard processor system
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17-866
Current_Host_Receive_Descriptor
Current_Host_Transmit_Descriptor Fields
Bit
31:0
curtdesaptr
Current_Host_Receive_Descriptor
The Current Host Receive Descriptor register points to the start address of the current Receive Descriptor
read by the DMA.
Module Instance
emac0
emac1
Offset:
0x104C
Access:
RO
31
30
15
14
Current_Host_Receive_Descriptor Fields
Bit
31:0
currdesaptr
Current_Host_Transmit_Buffer_Address
The Current Host Transmit Buffer Address register points to the current Transmit Buffer Address being
read by the DMA.
Module Instance
emac0
emac1
Altera Corporation
Name
Cleared on Reset. Pointer updated by the DMA
during operation.
29
28
27
26
13
12
11
10
Name
Cleared on Reset. Pointer updated by the DMA
during operation.
Description
Base Address
0xFF700000
0xFF702000
Bit Fields
25
24
23
22
currdesaptr
RO 0x0
9
8
7
6
currdesaptr
RO 0x0
Description
Base Address
0xFF700000
0xFF702000
Access
Register Address
0xFF70104C
0xFF70304C
21
20
19
18
5
4
3
2
Access
Register Address
0xFF701050
0xFF703050
Ethernet Media Access Controller
cv_5v4
2016.10.28
Reset
RO
0x0
17
16
1
0
Reset
RO
0x0
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