Altera cyclone V Technical Reference page 2076

Hard processor system

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Receive_Interrupt_Watchdog_Timer

This register, when written with non-zero value, enables the watchdog timer for the Receive Interrupt (Bit

6) of Register 5 (Status Register)

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Receive_Interrupt_Watchdog_Timer Fields

AXI_Bus_Mode

The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly used to control the burst

splitting and the number of outstanding requests.

Ethernet Media Access Controller

Send Feedback

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

This bit indicates the number of system clock cycles

multiplied by 256 for which the watchdog timer is set.

The watchdog timer gets triggered with the

programmed value after the Rx DMA completes the

transfer of a frame for which the RI status bit is not

set because of the setting in the corresponding

descriptor RDES1[31]. When the watchdog timer

runs out, the RI bit is set and the timer is stopped. The

watchdog timer is reset when the RI bit is set high

because of automatic setting of RI as per RDES1[31]

of any received frame.

Receive_Interrupt_Watchdog_Timer

Base Address

Altera Corporation

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