Altera cyclone V Technical Reference page 2073

17-858
Interrupt_Enable
Bit
8
rse
7
rue
6
rie
5
une
4
ove
Altera Corporation
Name
When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Receive Stopped
Interrupt is enabled. When this bit is reset, the
Receive Stopped Interrupt is disabled.
Value
0x0
0x1
When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Receive Buffer Unavail‐
able Interrupt is enabled. When this bit is reset, the
Receive Buffer Unavailable Interrupt is disabled.
When this bit is set with Normal Interrupt Summary
Enable (Bit 16), the Receive Interrupt is enabled.
When this bit is reset, the Receive Interrupt is
disabled.
Value
0x0
0x1
When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Transmit Underflow
Interrupt is enabled. When this bit is reset, the
Underflow Interrupt is disabled.
Value
0x0
0x1
When this bit is set with Abnormal Interrupt
Summary Enable (Bit 15), the Receive Overflow
Interrupt is enabled. When this bit is reset, the
Overflow Interrupt is disabled.
Value
0x0
0x1
Description
Description
Receive Stopped Interrupt Disabled
Receive Stopped Interrupt Enabled
Description
Receive Interrupt Disabled
Receive Interrupt Enabled
Description
Underflow Interrupt Disabled
Underflow Interrupt Enabled
Description
Transmit Overflow Interrupt Disabled
Transmit Overflow Interrupt Enabled
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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