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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
16.4 Port Control Register
Figure 16.4.1 shows the port control register.
When the P1 register is read after setting the PCR0 bit in the PCR register to "1", the corresponding port
latch can be read no matter how the PD1 register is set.
16.5 Pin Assignment Control register (PACR)
Figure 16.5.1 shows the PACR. After reset set the PACR2 to PACR0 bit before you input and output it to
each pin. When the PACR register isn't set up, the input and output function of some of the pins doesn't
work.
PACR2 to PACR0 bits: control the pins enabled for use.
At reset, these bits are "000".
In 48-pin package, set these bits to "100
In 42-pin package, set these bits to "001
U1MAP: controls the assignment of UART1 pins.
If the U1MAP bit is set to "0" (P6
P6
/CLK
, P6
5
1
If the U1MAP bit is set to "1" (P7
P7
/CLK
, P7
1
1
PACR is write protected by PRC2 bit in the PRCR register. PRC2 bit must be set immediately before the
write to PACR.
16.6 Digital Debounce function
Two digital debounce function circuits are provided. Level is determined when level is held, after applying
either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables
noise reduction.
This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and
the P17DDR register respectively. Additionally, a digital debounce function is disabled to the port P1
input and port P8
Filter width :
The NDDR register and the P17DDR register decrement count value with f8 as the count source. The
NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or
a rising edge is applied to the pin.
The NDDR register and the P17DDR register can be set 00
function. Setting to FF
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
7
/RxD
, and P6
/TxD
6
1
7
3
/RxD
, and P7
/TxD
2
1
3
________
input. Figure 16.6.1 shows the NDDR register and the P17DDR register.
5
(n+1) × 1/ f8 n: count value set in the NDDR register and P17DDr register
disables the digital filter. See Figure 16.6.2 for details.
16
page 217
f o
3
2
9
6
C
2 /
6
) T
".
2
".
2
to P6
) the UART1 functions are mapped to P6
4
.
1
to P7
) the UART1 functions are mapped to P7
0
.
1
_______ _____
to FF
16
16. Programmable I/O Ports
/CTS
4
/CTS
0
when using the digital debounce
16
/RTS
,
1
1
/RTS
,
1
1
7
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