M16C/29 Group
2
16.4.5 Bit 7: I
This bit selects the input level of the S
set to "1", the P2
0
The signal of writing "1" to IHR bit
The reset signal to I
Figure 16.10 The timing of reset to the I
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
C bus interface pin input level select bit (TISS)
CL
and P2
become the SMBus input level.
1
IHR bit
2
C bus interface circuit
2
page 260 of 402
and S
pins of the multi-master I
DA
2.5 V
IIC
C bus interface circuit
2
16. MULTI-MASTER I
2
C bus interface. When this bit is
cycles
C bus INTERFACE