Normal Space Interface - Renesas RZ/A Series User Manual

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Table of Contents

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Normal Space Interface

(1) Basic Timing

For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will

be directly connected. When using SRAM with a byte-selection pin, see section 8.5.8, SRAM Interface with Byte

Selection. Figure 8.2 shows the basic timings of normal space access. A no-wait normal access is completed in two

cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle.

Normal Space Basic Access Timing (Access Wait 0)

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

Note: * The waveform for DACKn is when active low is specified.

8. Bus State Controller

Rz/a1 series Rz/a1lu series Rz/a1lc series