Axi Protocol Control Signals; Bus Masters Other Than Cortex-A9, Coresight, And The Direct Memory Access Controller; Cortex-A9; Coresight - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.8

AXI Protocol Control Signals

The AXI protocol control signals can be set as desired for each bus master. For details of the AXI protocol control
signals, refer to the AMBA AXI Protocol Specification prepared by Arm Ltd.
5.8.1 Bus Masters other than Cortex-A9, CoreSight, and the Direct Memory Access
Controller
(1) Cache Control Signals (ARCACHE[3:0] and AWCACHE[3:0])
Use the AXI bus control register (AXIBUSCTL) to make settings of the ARCACHE[3:0] and AWCACHE[3:0] signals
for each bus master. Be sure to make settings while the target bus master does not use the AXI bus.
(2) Response Signals (RRESP[1:0] and BRESP[1:0])
Use the AXI bus response error status register (AXIRERRST) to read the RRESP[1:0] and BRESP[1:0] signals received
by each bus master. The register value is updated when a response error occurs. The status register value can be cleared
to 00 through the AXI bus response error clear register (AXIRERRCLR).
In addition, enabling interrupts through the AXI bus response error interrupt control register (AXIRERRCTL) allows an
interrupt to be generated when a response error occurs.
This interrupt should be used only for debugging purposes. Make sure that no response error occurs during system
operation.
(3) Protection unit information (ARPROT[2:0], AWPROT[2:0])
Signals ARPROT[2:0] and AWPROT[2:0] are fixed as follows and cannot be modified.
ARPROT[2], AWPROT[2]: 0 (data access)
ARPROT[1], AWPROT[1]: 1*(non-secure access)
ARPROT[0], AWPROT[0]: 0 (normal access)
Note: * For the EthernetAVB, signals ARPROT[1] and AWPROT[1] are fixed to 0 (secure access).
(4) Atomic access (ARLOCK[1:0], AWLOCK[1:0])
Signals ARLOCK[1:0] and AWLOCK[1:0] are fixed as follows and cannot be modified.
ARLOCK[1:0], AWLOCK[1:0]: 00 (normal access)
5.8.2

Cortex-A9

For details on the Cortex-A9, refer to the Arm Architecture Reference Manual.
5.8.3

CoreSight

For details on CoreSight, refer to the technical reference manual issued by Arm Ltd.
The bus master side (AHB access port) of CoreSight is connected to the main bus via the AHB-AXI bus conversion
circuit.
The signals are converted as follows for connection to the AXI bus.
(1) Cache control (ARCACHE[3:0], AWCACHE[3:0])
ARCACHE[3], AWCACHE[3]: 0 when HPROT[3] is 0, 1 when HPROT[3] is 1.
ARCACHE[2], AWCACHE[2]: 0 when HPROT[3] is 0, 1 when HPROT[3] is 1.
ARCACHE[1], AWCACHE[1]: Value of HPROT[3] (cacheable)
ARCACHE[0], AWCACHE[0]: Value of HPROT[2] (bufferable)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
5. LSI Internal Bus
5-12