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M16C/29 Group
9.4.1 Interrupt Response Time
Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge
time denotes time from when an interrupt request is generated till when the first instruction in the
interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is
generated till when the instruction then executing is completed ((a) in Figure 9.4.1.1) and the time
during which the interrupt sequence is executed ((b) in Figure 9.4.1.1).
Interrupt request generated
(a) The time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) The time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Figure 9.4.1.1. Interrupt response time
9.4.2 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 9.4.2.1 is set in the IPL. Shown in Table 9.4.2.1 are the IPL values of software and
special interrupts when they are accepted.
Table 9.4.2.1. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Watchdog timer, NMI, Oscillation stop and re-oscillation detection,
voltage down detection
Software, address match, DBC, single-step
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Interrupt request acknowledged
Instruction
Interrupt sequence
(a)
Interrupt response time
Interrupt vector address
Even
Even
Odd
Odd
_______
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interrupt routine
(b)
SP value
Without wait
Even
18 cycles
Odd
19 cycles
Even
19 cycles
Odd
20 cycles
Time
Instruction in
Level that is set to IPL
Not changed
9. Interrupts
7
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