Interrupt Response Time; Periods When Interrupts Cannot Be Acknowledged; Example Of Pipeline Operation When Interrupt Request Is Acknowledged (Outline) - Renesas NU85E Preliminary User's Manual

8.6 Interrupt Response Time

Except in the following cases, the interrupt response time is a minimum of 5 clocks. To input interrupt requests
continuously, leave a space of at least 5 clocks between interrupt request inputs.
• During software or hardware STOP mode
• When an external bus is accessed
• When there are two or more successive interrupt request non-sampling instructions (see 8.7 Periods When
Interrupts Cannot Be Acknowledged).
• When the interrupt control register is accessed
Figure 8-16. Example of Pipeline Operation When Interrupt Request Is Acknowledged (Outline)
Interrupt acknowledgement operation
Instruction (first instruction of
interrupt service routine)
Remark INT1 to INT4: Interrupt acknowledgement servicing
IFx: Invalid instruction fetch
IDx: Invalid instruction decode

8.7 Periods When Interrupts Cannot Be Acknowledged

An interrupt is acknowledged while an instruction is being executed. However, an interrupt is not acknowledged
between an interrupt request non-sampling instruction and the subsequent instruction (the interrupt is held pending).
The interrupt request non-sampling instructions are as follows.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• Store instruction for specific area (xFFF100H to xFFF1FFH
Note The IMR0 to IMR3, PIC0 to PIC63, ISPR, PRCMD, and PSC registers are allocated to a part of this area.
CHAPTER 8 INTC
VBCLK (Input)
Interrupt request
Instruction 1 IF ID
Instruction 2 IFx
Preliminary User's Manual A14874EJ3V0UM
5 system clocks
EX MEM WB
IDx
INT1 INT2 INT3 INT4
IF ID
Note
, xFFF900H to xFFF9FFH)
EX
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