Interrupt Response Time - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

Interrupt Response Time

Figure 1.10.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) in Figure 1.10.6) and a time during which the interrupt
sequence is executed ((b) in Figure 1.10.6).
Interrupt request generated
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address
Even
Odd
Figure 1.10.6 Interrupt response time
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 1.10.5 is set in the IPL. Table 1.10.5 shows the IPL values of software and special interrupts
when they are accepted.
Table 1.10.5 IPL Level that is Set to IPL When A Software or Special Interrupt is Accepted
Oscillation stop and re-oscillation detection, Watchdog timer, NMI
Software, address match, DBC, single-step
Rev.1.00 2003.05.30 page 76
Interrupt request acknowledged
Instruction Interrupt sequence
(a)
Interrupt response time
SP value
Even
Odd
Even
Odd
Interrupt sources
_________
Instruction in
interrupt routine
(b)
16-bit bus, without wait
18 cycles
19 cycles
19 cycles
20 cycles
_______
Interrupts
Time
8-bit bus, without wait
20 cycles
Value set in the IPL
7
Not changed