Chapter 5
Interrupt
5.3.1 Interrupt Response Time
Figure 5.3.2 shows the interrupt resonse time. The interrupt response time means a period of time from
when an interrupt request is generated till when the first instruction of the interrupt routine is executed.
This period consists of time ((a) into Figure 5.3.1) from when an interrupt request is generated to when
the instruction then under way is completed and time (20 cycles (b)) in which an interrupt sequence is
executed.
Interrupt request generated
(a) Time from when interrupt request is generated to when the instruction then under execution is
completed. Time (a) varies with each instruction being executed. The DIVX instruction requires
a maximum time that consists of 30 cycles (without wait state, cycle number in case the
divisor is register ).
(b) The address-match interrupt and the single-step interrupt are 21 cycles.
Figure 5.3.2 Interrupt response time
5.3.2 Changes of IPL When Interrupt Request Acknowledged
When an interrupt request of maskable instruction is acknowledged, the interrupt priority level of the
acknowledged interrupt is set to the IPL.
When an software interrupt request or an special interrupt request is acknowledged, the value shown in
Table 5.3.1 is set to the IPL. Table 5.3.1 shows the value of IPL when software interrupt and special
interrupt request acknowledged.
Table 5.3.1 Value of IPL when software interrupt and special interrupt request acknowledged
Interrupt sources without interrupt priority levels
Watchdog timer, Oscillation stop detection
Software, Address-match, Single-step
Interrupt request acknowledged
Instruction
Interrupt sequence
20 cycles (b)
(a)
Interrupt response time
Instruction in interrupt
routine
Value that is set to IPL
253
5.3 Interrupt Sequence
Time
7
Not changed