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•
A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an
exception sequence.
The RAM array contains 64 words of 32 bits each. The signal timing generator loads the RAM word from
the RAM array to drive the general-purpose lines and chip-selects. If the UPM reads a RAM word with
WAEN set, the external UPWAIT signal is sampled and synchronized by the memory controller and the
current request is frozen.
21.4.4.1
UPM Requests
A special pattern location in the RAM array is associated with each of the possible UPM requests. An
internal device's request for a memory access initiates one of the following patterns (MxMR[OP] = 00):
•
Read single-beat pattern (RSS)
•
Read burst cycle pattern (RBS)
•
Write single-beat pattern (WSS)
•
Write burst cycle pattern (WBS)
A UPM refresh timer request pattern initiates a refresh timer pattern (RTS).
An exception (caused by a bus monitor time-out error) occurs while another UPM pattern is running
initiates an exception condition pattern (EXS).
Figure 21-35
and
Table 21-71
cycle type. RUN commands (MxMR[OP] = 11), however, can initiate patterns starting at any of the 64
UPM RAM words.
Read Single-Beat Request
Read Burst Request
Write Single-Beat Request
Write Burst Request
Refresh Timer Request
Exception Condition Request
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
show the start addresses of these patterns in the UPM RAM, according to
Array Index
Generator
Figure 21-35. RAM Array Indexing
External Memory Controller (EMC)
RSS
RBS
WSS
RAM Array
WBS
RTS
EXS
64 RAM
Words
21-67
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