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External Memory Controller (EMC)
LCLK
LALE
LCS1
LCS2
LCS3
LCS4
LSDRAS
LSDCAS
LSDWE
LSDDQM
LAD[23:0]
TA
21.4.4
User-Programmable Machines (UPMs)
The user-programmable machines (UPMs) are flexible interfaces that connect to a wide range of memory
devices. At the heart of each UPM is an internal RAM array that specifies the logical value driven on the
external memory control signals (LCSx, and LGPL[5:0]) for a given clock cycle. Each word in the RAM
array provides bits that allow a memory access to be controlled with a resolution of up to one quarter of
the external bus clock period on the chip-select lines.
UPM.
Memory Access Request
(issued in software)
Exception Request
UPWAIT
Figure 21-34. User-Programmable Machine Functional Block Diagram
The following events initiate a UPM cycle:
•
Any internal device requests an external memory access to an address space mapped to a
chip-select serviced by the UPM.
•
A UPM refresh timer expires and requests a transaction, such as a DRAM refresh.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-66
Auto
Auto
Auto
Auto
Ref
Ref
Ref
Ref
Z
Figure 21-33. SDRAM Bank-Staggered Auto Refresh Timing
Internal / External
UPM Refresh
Timer Request
Generator
Run Command
Wait
Hold
Request
Logic
WAEN Bit
SDMR[RFCR]
1111
ROW ADD
Figure 21-34
Array
Index
Index
Increment
Index
Internal
(LAST = 0)
Signals
Latch
Internal Controls
Activate
0000
1111
X
COL ADD
D0
Z
shows the basic operation of each
RAM Array
Signals
Timing
Generator
LGPLx
LCSx
Freescale Semiconductor
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