Input Pins; Register Description - Renesas H8S/2100 Series Hardware Manual

15.2

Input Pins

Table 15.1 shows the input pin of the CIR.
Table 15.1 Pin Configuration
Pin Name
CIR input pin
15.3

Register Description

Table 15.2 shows the CIR register configuration.
Table 15.2 List of Register Addresses
Register Name
Receive control register 1
Receive control register 2
Receive status register
Interrupt enable register
Bit rate register
Receive data register 0 to 7
Header minimum high-level period register
Header maximum high-level period register HHMAX
Header minimum low-level period register
Header maximum low-level period register
Data level 0 minimum period register
Data level 0 maximum period register
Data level 1 minimum period register
Data level 1 maximum period register
Symbol I/O
CIRI Input
Abbreviation
CCR1
CCR2
CSTR
CEIR
BRR
CIRRDR0 to
CIRRDR7
HHMIN
HLMIN
HLMAX
DT0MIN
DT0MAX
DT1MIN
DT1MAX
Section 15 CIR Interface
Function
CIR receive data input pin
R/W Initial Value
R/W H'04
R/W H'00
R/W H'00
R/W H'00
R/W H'FF
R H'00
R/W H'0000
R/W H'0000
R/W H'00
R/W H'00
R/W H'00
R/W H'00
R/W H'00
R/W H'00
Rev. 1.00 May 09, 2008 Page 431 of 954
Address
H'FA40
H'FA41
H'FA42
H'FA43
H'FA44
H'FA45
H'FA46
H'FA48
H'FA4A
H'FA4B
H'FA4C
H'FA4D
H'FA4E
H'FA4F
REJ09B0462-0100