Relation Between Dmac And External Bus Requests And Refresh Cycles; Figure 7.34 Example Of Multi-Channel Transfer - Renesas H8S/2368 Series Hardware Manual

DMA read
Address bus
DMA control
Idle Read
Channel 0A Request clear
Channel 0B
Channel 1
Bus
release
7.5.13

Relation between DMAC and External Bus Requests and Refresh Cycles

When the DMAC accesses external space, conflict with a refresh cycle or external bus release
cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle
or external bus release cycle, in accordance with the external bus priority order, even if the DMAC
is executing a burst transfer or block transfer. (An external access by the DTC or CPU, which has
a lower priority than the DMAC, is not executed until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
cycle may be executed at the same time as a refresh cycle or external bus release cycle.
DMA write
Write Idle
Request clear
Request Selection
hold
Request
Non-
selection
hold
Channel 0A Bus
transfer release

Figure 7.34 Example of Multi-Channel Transfer

DMA read DMA write
Read Write Idle
Request
Selection
hold
Channel 0B
transfer
DMA read DMA write
Read Write
Request clear
Channel 1 transfer
Bus
release
Rev. 2.00, 05/03, page 265 of 820
DMA
read
Read