External Bus Requests, Refresh Controller, And Dmac - Renesas F-ZTAT H8 Series Hardware Manual

Section 8 DMA Controller
DMAC cycle
(channel 1)
T
1
φ
Address
bus
RD
HWR
,
LWR
Figure 8.19 Timing of Multiple-Channel Operations
8.4.10

External Bus Requests, Refresh Controller, and DMAC

During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the refresh controller, the DMAC releases the bus after completing the transfer of the current
byte or word. If there is a transfer request at this point, the DMAC requests the bus right again.
Figure 8.20 shows an example of the timing of insertion of a refresh cycle during a burst transfer
on channel 0.
T T
1
φ
Address
bus
RD
HWR LWR
,
Figure 8.20 Bus Timing of Refresh Controller and DMAC
Rev. 7.00 Sep 21, 2005 page 246 of 878
REJ09B0259-0700
CPU
cycle
T T T T T
2 1 2 d
DMAC cycle (channel 0)
T T T T
2 1 2 1 2
DMAC cycle CPU
(channel 0A) cycle
T T T T
1 2 1 2 1
Refresh
cycle
T T T T T
1 2 1 2 d
DMAC cycle
(channel 1)
T T T T T
2 d 1 2 1
DMAC cycle (channel 0)
T T T T T
1 2 1 2 1
T
2
T
2