External Bus Interface - Renesas H8SX/1650 Hardware Manual

Bφ
CS5
CS6
Output waveform
Address bus
Figure 6.9 Timing When CS Signal is Output to the Same Pin
6.5.4

External Bus Interface

The type of the external bus interfaces, bus width, endian format, number of access cycles, and
strobe assert/negate timings can be set for each area in the external address space. The bus width
and the number of access cycles for both on-chip memory and internal I/O registers are fixed, and
are not affected by the external bus settings.
(1)
Type of External Bus Interface
Four types of external bus interfaces are provided and can be selected in area units. Table 6.4
shows each interface name, description, and area name to be set for each interface. Table 6.5
shows the areas that can be specified for each interface. The initial state of each area is a basic bus
interface.
Table 6.4 Interface Names and Area Names
Interface
Basic interface
Byte control SRAM
interface
Burst ROM interface
Address/data multiplexed
I/O interface
Area 5 access
Area 5 access
Description
Directly connected to ROM and RAM
Directly connected to byte SRAM with
byte control pin
Directly connected to the ROM that
allows page access
Directly connected to the peripheral
LSI that requires address and data
multiplexing
Section 6 Bus Controller (BSC)
Area 6 access
Area 6 access
Area Name
Basic bus space
Byte control SRAM space
Burst ROM space
Address/data multiplexed I/O
space
Rev.2.00 Jun. 28, 2007 Page 155 of 666
REJ09B0311-0200