Idle Mode - Renesas H8S Series Hardware Manual

7.5.3

Idle Mode

Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is
transferred in response to a single transfer request, and this is executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in
DMACR.
Table 7-7 summarizes register functions in idle mode.
Table 7-7 Register Functions in Idle Mode
Register
23
23 15
H'FF
15
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR:Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor
decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Figure 7-5 illustrates operation in idle mode.
MAR
DTDIR = 0 DTDIR = 1 Initial Setting
0
Source
address
MAR
register
0 Destination
address
IOAR
register
0 Transfer counter
ETCR
Figure 7-5 Operation in Idle Mode
Function
Destination Start address of
address transfer destination
register or transfer source
Source Start address of
address transfer source or
register transfer destination
Number of transfers Decremented every
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Operation
Fixed
Fixed
transfer; transfer
ends when count
reaches H'0000
IOAR
Rev.6.00 Oct.28.2004 page 199 of 1016
REJ09B0138-0600H