Byte Access Control - Renesas H8S Series Hardware Manual

6.5.9

Byte Access Control

When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for
byte access.
When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the control timing in the 2-
CAS system, and figure 6-19 shows an example 2-CAS system DRAM connection.
When only DRAM with a ×8 configuration is connected, set the CW2 bit to 1 in MCR.
Byte control
Note: n = 2 to 5
Figure 6-18 2-CAS System Control Timing (Upper Byte Write Access)
T
p
ø
A to A
23 0
CSn, (RAS)
CAS
LCAS
HWR, (WE)
H8S/2357 Group
(Address shift size set to 9 bits)
CS, (RAS)
CAS
LCAS
HWR, (WE)
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
D to D
15 0
Figure 6-19 Example of 2-CAS System Connection
T T
r c1
Row Column
2-CAS type 4-Mbit DRAM
256-kbyte x 16-bit configuration
9-bit column address
RAS
UCAS
LCAS
WE
A Low address
8
input: A
8
A
7
Column address
A
6
input: A
8
A
5
A
4
A
3
A
2
A
1
A
0
D to D
15 0
OE
Rev.6.00 Oct.28.2004 page 143 of 1016
T
c2
to A
0
to A
0
REJ09B0138-0600H