VPA13 to VPA0
(Output)
VPDO15 to VPDO8
(Output)
VPDI15 to VPDI8
(Input)
VPDO7 to VPDO0
(Output)
VPDI7 to VPDI0
(Input)
VPWRITE (Output)
VPSTB (Output)
VPUBENZ (Output)
VPLOCK (Output)
VPRETR (Input)
L
Figure 5-10. Timing of Byte Access to Even Address
VPA13 to VPA0
(Output)
VPDO15 to VPDO8
(Output)
VPDI15 to VPDI8
(Input)
VPDO7 to VPDO0
(Output)
VPDI7 to VPDI0
(Input)
VPWRITE (Output)
VPSTB (Output)
VPUBENZ (Output)
VPLOCK (Output)
VPRETR (Input)
L
CHAPTER 5 BBR
Figure 5-9. Timing of Byte Access to Odd Address
Write cycle
A.0
D.0
Write cycle
A.0
D.0
Preliminary User's Manual A14874EJ3V0UM
Read cycle
A.1
D.1
Read cycle
A.1
D.1
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