Csn Space Wait Control Register (Csnwcr) (N = 0 To 5) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.4.3

CSn Space Wait Control Register (CSnWCR) (n = 0 to 5)

CSnWCR specifies various wait cycles for memory access. The bit configuration of this register varies as shown below
according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR). Specify
CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR.
(1) Normal Space, SRAM with Byte Selection, and MPX-I/O
• CS0WCR
Bit: 31
-
Initial value: 0
R/W:
R
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
31 to 22 ―
21 ―*
20 BAS
19, 18 ―
17, 16 ―*
15 to 13 ―
12, 11 SW[1:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - SW[1:0]
0 0 0 0 1
R R R/W R/W R/W
Initial
Value R/W
All 0 R
0 R/W
0 R/W
All 0 R
All 0 R/W
All 0 R
00 R/W
25 24 23 22 21
- - - - -*
0 0 0 0 0
R R R R R/W
9 8 7 6 5
WR[3:0] WM -
0 1 0 0 0
R/W R/W R/W R/W R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Reserved
Set this bit to 0 when the interfaces for normal space or for SRAM with
byte selection are used.
SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the SRAM interface
with byte selection is used.
0: Asserts the WEn signal at the read/write timing and asserts the RD/WR
signal during the write access cycle.
1: Asserts the WEn signal during the read/write access cycle and asserts
the RD/WR signal at the write timing.
Reserved
These bits are always read as 0. The write value should always be 0.
Reserved
Set these bits to 0 when the interfaces for normal space or for SRAM with
byte selection are used.
Reserved
These bits are always read as 0. The write value should always be 0.
Number of Delay Cycles from Address, CS0 Assertion to RD, WEn
Assertion
Specify the number of delay cycles from address and CS0 assertion to RD
and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
8. Bus State Controller
20 19 18 17 16
BAS - - -* -*
0 0 0 0 0
R/W R R R/W R/W
4 3 2 1 0
- - - HW[1:0]
0 0 0 0 0
R R R R/W R/W
8-10