Interrupt Sources; Nmi Interrupt; Irq Interrupts - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
7.4

Interrupt Sources

There are four types of interrupt sources: NMI, IRQ, on-chip peripheral modules, and pin interrupts. Each interrupt has a
priority level (0 to 31), with 0 the highest and 31 the lowest.
7.4.1

NMI Interrupt

The NMI interrupt with the highest priority is accepted by the CPU as an FIQ exception all times. NMI interrupt requests
are edge-detected, and the NMI edge select bit (NMIE) in ICR0 selects whether the rising edge or falling edge is
detected. The status of the interrupt request can be checked by reading the NMI interrupt request bit (NMIF) in the ICR0.
When the NMIE bit is changed, the NMI interrupt request that is retained is cleared.
When deep standby mode is entered, deep standby mode is canceled by the NMI interrupt.
7.4.2

IRQ Interrupts

IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge, rising-edge, or both-
edge detection can be selected individually for each pin by the IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S to
IRQ00S) in interrupt control register 1 (ICR1).
When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the interrupt controller while the
IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the interrupt controller when the IRQ7 to
IRQ0 pins are driven high. The status of the interrupt requests can be checked by reading the IRQ interrupt request bits
(IRQ7F to IRQ0F) in the IRQ interrupt request register (IRQRR).
When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the IRQ7 to IRQ0 pin
states, and an interrupt request signal is sent to the interrupt controller. The result of IRQ interrupt request detection is
retained until that interrupt request is accepted. Whether IRQ interrupt requests have been detected or not can be checked
by reading the IRQ7F to IRQ0F bits in the IRQ interrupt request register (IRQRR). Writing 0 to these bits after reading
them as 1 clears the result of IRQ interrupt request detection.
When returning from IRQ interrupt exception service routine, execute the return instruction after confirming that the
interrupt request has been cleared by the IRQ interrupt request register (IRQRR) so as not to accidentally receive the
interrupt request again.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
7. Interrupt Controller
7-16