Receiver; Figure 231. Tc/Txe Behavior When Transmitting - STMicroelectronics STM32F05 series Reference Manual

RM0091

Figure 231. TC/TXE behavior when transmitting

Idle preamble
TX line
TXE flag
USART_DR
F1
TC flag
software
software waits until TXE=1
enables the
and writes F2 into DR
USART
software waits until TXE=1
and writes F1 into DR
Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the
M bit (see
If a '1' is written to the SBKRQ bit, a break character is sent on the TX line after completing
the current character transmission. The SBKF bit is set by the write operation and it is reset
by hardware when the break character is completed (during the stop bits after the break
character). The USART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of
the break frame to guarantee the recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.
25.5.3

Receiver

The USART can receive data words of either 8 or 9 bits depending on the M bit in the
USART_CR1 register.
Start bit detection
The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized.
This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.
Universal synchronous asynchronous receiver transmitter (USART)
Frame 1
set by hardware
cleared by software
F2
software waits until TXE=1
and writes F3 into DR
Figure 229).
Doc ID 018940 Rev 1
Frame 2
set by hardware
cleared by software
F3
TC is not set TC is not set
because TXE=0 because TXE=0
software waits until TC=1
Frame 3
set by hardware
TC is set because
TXE=1
set
by hardware
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