Error Handling; Bit Error; Message Error; Bit Rising Error (Bre) - STMicroelectronics STM32F05 series Reference Manual

HDMI-CEC controller (HDMI-CEC)
SFTOPT=1 bus-event condition starting the SFT timer is detected in the following cases:
●
In case of a regular end of transmission/reception, when TXEND/RXEND bits are set at
the minimum nominal data bit duration of the last bit in the message (ACK bit).
●
In case of a transmission error detection, SFT timer starts when the TXERR
transmission error is detected (TXERR=1).
● In case of a missing acknowledge from the CEC follower, the SFT timer starts when the
TXACKE bit is set, that is at the nominal sampling time of the ACK bit.
●
In case of a transmission underrun error, the SFT timer starts when the TXUDR bit is
set at the end of the ACK bit.
●
In case of a receive error detection implying reception abort, the SFT timer starts at the
same time the error is detected. If an error bit is generated, then SFT starts being
counted at the end of the error bit.
●
In case of a wrong start bit or of any un-codified low impedance bus state from idle, the
SFT timer is restarted as soon as the bus comes back to hi-impedance idleness.
28.5

Error handling

28.5.1

Bit error

If a data bit - excluding the start bit - is considered invalid, the follower is expected to notify
such error by generating a low bit period on the CEC line of 1.4 to 1.6 times the nominal
data bit period, i.e. 3.6 ms nominally.

Figure 296. Error bit timing

ERROR BIT
28.5.2

Message error

A message is considered lost and therefore may be retransmitted under the following
conditions:
● a message is not acknowledged in a directly addressed message
●
a message is negatively acknowledged in a broadcast message
● a low impedance is detected on the CEC line while it is not expected (line error)
Three kinds of error flag can be detected when the CEC interface is receiving a data bit:
28.5.3

Bit Rising Error (BRE)

BRE (bit rising error): is set when a bit rising edge is detected outside the windows where it
is expected (see
In the case of a BRE detection, the message reception can be stopped according to the
BRESTP bit value and an error bit can be generated if BREGEN bit is set.
704/742
high impedance
low impedance
Figure 297). BRE flag also generates a CEC interrupt if the BREIE=1.
Doc ID 018940 Rev 1
3.6ms +/-0.24ms
RM0091