STMicroelectronics STM32F05 series Reference Manual page 445

RM0091
Figure 188. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
Figure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
preloaded)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
Write a new value in TIMx_ARR
Doc ID 018940 Rev 1
31 32 33 34 35 36 00 01 02 03 04 05 06 07
FF
F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
F5
F5
Basic timer (TIM6)
36
36
36
445/742