Reset and clock control (RCC)
7.4.15
RCC register map
The following table gives the RCC register map and the reset values.
Table 19.
RCC register map and reset values
Offset
Register
RCC_CR
0x00
Reset value
RCC_CFGR
0x04
Reset value
RCC_CIR
0x08
Reset value
RCC_APB2RSTR
0x0C
Reset value
RCC_APB1RSTR
0x010
Reset value
RCC_AHBENR
0x14
Reset value
RCC_APB2ENR
0x18
Reset value
RCC_APB1ENR
0x1C
Reset value
RCC_BDCR
0x20
Reset value
RCC_CSR
0x24
Reset value
0
116/742
0
0
MCO [2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Doc ID 018940 Rev 1
HSICAL[7:0]
0
0
0
0
0
0
0
PLLMUL[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSITRIM[4:0]
0
0
0
0
0
1
0
0
0
PPRE
HPRE[3:0]
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
RTC
SEL
DRV
[1:0]
[1:0]
0
0
0
RM0091
0
1
1
SWS
SW
[1:0]
[1:0]
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
LSE
0
0
0
0
0
0
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