Transmission Error Detection (Txerr); Table 104. Txerr Timing Parameters; Figure 298. Txerr Detection - STMicroelectronics STM32F05 series Reference Manual

RM0091
28.5.6

Transmission Error Detection (TXERR)

The CEC initiator sets the TXERR flag if detecting low impedance on the CEC line when it is
transmitting high impedance and is not expecting a follower asserted bit. TXERR flag also
generates a CEC interrupt if the TXERRIE=1.
TXERR assertion stops the message transmission. Application is in charge to retry the
failed transmission up to 5 times.
TXERR checks are performed differently depending on the different states of the CEC line
and on the RX tolerance configuration.

Figure 298. TXERR detection

Legend:

Table 104. TXERR timing parameters

Time
T
s
T
1
T
n1
T
2
T
ns
T
3
TXERR Checking Window
Tx data bit-1
T T T T
s 1 n1 2
RXTOL
x
1
0
x
0
1
x
1
0
Doc ID 018940 Rev 1
HDMI-CEC controller (HDMI-CEC)
CEC initiator bit-timing
Tx acknowledge
Tx arbitration bit-1
T T T T
ns 3 n0
Tx arbitration bit-0
Tx data bit-0
ms
0 Bit start event.
0.3
The earliest time for a low - high transition when
indicating a logical 1.
0.4
The nominal time for a low - high transition when
0.6
indicating a logical 1.
0.8
The latest time for a low - high transition when
indicating a logical 1.
0.9
1.05 Nominal sampling time.
1.2
The earliest time a device is permitted return to a
high impedance state (logical 0).
1.3
Tolerance margins
T T
4 5 nf
Description
T
6
707/742