Timer Synchronization (Tim15); Debug Mode; Figure 180. Control Circuit In Trigger Mode - STMicroelectronics STM32F05 series Reference Manual

RM0091
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
●
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don't need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don't need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register.
Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level
only).
●
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 180. Control circuit in trigger mode

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 16.3.15: Timer synchronization on page 323
18.4.15

Timer synchronization (TIM15)

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Refer to
18.4.16

Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. .
cnt_en
Counter clock = ck_cnt = ck_psc
Counter register
Section 13.3.15: Timer synchronization on page 308
Doc ID 018940 Rev 1
General-purpose timers (TIM15/16/17)
TI2
34
TIF
35 36 37 38
for details.
for details.
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