Figure 71. Output Stage Of Capture/Compare Channel (Channel 1 To 3); Figure 72. Output Stage Of Capture/Compare Channel (Channel 4) - STMicroelectronics STM32F05 series Reference Manual

RM0091

Figure 71. Output stage of capture/compare channel (channel 1 to 3)

ETR
CNT>CCR1
CNT=CCR1

Figure 72. Output stage of capture/compare channel (channel 4)

ETR
CNT > CCR4
CNT = CCR4
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
OC1REF
Output mode
controller
OC1CE OC1M[2:0]
TIM1_CCMR1
OC4 REF
Output mode
controller
OC2M[2:0]
TIM1_CCMR2
Doc ID 018940 Rev 1
'0'
x0
10
OC1_DT
11
Dead-time
generator
OC1N_DT
11
10
'0'
0x
DTG[7:0] CC1NE CC1E
TIM1_BDTR TIM1_CCER
To the master mode
controller
Advanced-control timers (TIM1)
0
Output
enable
circuit
1
CC1P
TIM1_CCER
0
Output
enable
circuit
1
CC1NE CC1E TIM1_CCER
CC1NP MOE OSSI OSSR
TIM1_CCER
0
Output
enable
circuit
1
CC4P
TIM1_CCER
CC4E TIM1_CCER
MOE OSSI TIM1_BDTR
TIM1_CR2
OIS4
OC1
OC1N
TIM1_BDTR
OC4
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