STMicroelectronics STM32F05 series Reference Manual page 710

HDMI-CEC controller (HDMI-CEC)
Bit 0 CECEN: CEC Enable
The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the
TXSOM control. CECON=0 disables the CEC peripheral, clears all bits of CEC_CR register and
aborts any on-going reception or transmission.
0: CEC peripheral is off
1: CEC peripheral is on
710/742 Doc ID 018940 Rev 1
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