Tim2 And Tim3 Register Map; Table 50. Tim2 And Tim3 Register Map And Reset Values - STMicroelectronics STM32F05 series Reference Manual

RM0091
16.4.19

TIM2 and TIM3 register map

TIM2 and TIM3 registers are mapped as described in the table below:
Table 50. TIM2 and TIM3 register map and reset values
Offset Register
TIM2_CR1 and
TIM3_CR1
0x00
Reset value
TIM2_CR2 and
TIM3_CR2
0x04
Reset value
TIM2_SMCR and
TIM3_SMCR
0x08
Reset value
TIM2_DIER and
TIM3_DIER
0x0C
Reset value
TIM2_SR and
0x10 TIM3_SR
Reset value
TIM2_EGR and
0x14 TIM3_EGR
Reset value
TIM2_CCMR1
and
TIM3_CCMR1
Output compare
mode
Reset value
0x18
TIM2_CCMR1
and
TIM3_CCMR1
Input capture
mode
Reset value
TIM2_CCMR2
and
TIM3_CCMR2
Output compare
mode
Reset value
0x1C
TIM2_CCMR2
and
TIM3_CCMR2
Input capture
mode
Reset value
TIM2_CCER and
TIM3_CCER
0x20
Reset value
TIM2_CNT and
TIM3_CNT
0x24
Reset value 0
TIM2_PSC and
TIM3_PSC
0x28
Reset value
TIM2_ARR and
TIM3_ARR
0x2C
Reset value 0
CNT[31:16]
(TIM2 only)
0 0 0 0 0 0 0 0 0
ARR[31:16]
(TIM2 only)
0 0 0 0 0 0 0 0 0
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
ETPS
[1:0]
0 0 0
0
OC2M
[2:0]
0 0 0
IC2F[3:0]
0 0 0
OC4M
[2:0]
0 0 0
IC4F[3:0]
0 0 0
0 0
0 0 0 0 0 0 0 0 0
0 0 0
0 0 0 0 0 0 0 0 0
CKD CMS
[1:0] [1:0]
0 0 0 0 0 0
MMS[2:0]
0 0 0 0
ETF[3:0] TS[2:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0
0 0
CC2S OC1M
[1:0] [2:0]
0 0 0 0 0 0 0 0 0
IC2
CC2S
PSC IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0 0
CC4S OC3M
[1:0] [2:0]
0 0 0 0 0 0 0 0 0
IC4
CC4S
PSC IC3F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0
0
SMS[2:0]
0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
CC1S
[1:0]
0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0
CC3S
[1:0]
0 0 0 0
IC3
CC3S
PSC
[1:0]
[1:0]
0 0 0 0
0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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