STMicroelectronics STM32F05 series Reference Manual page 106

Reset and clock control (RCC)
Bit 31 Reserved, must be kept at reset value.
Bit 30 CECEN: HDMI CEC interface clock enable
Bit 29 DACEN: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Bit 27:24 Reserved, must be kept at reset value.
Bit 22 I2C2EN: I2C2 clock enable
Bit 21 I2C1EN: I2C1 clock enable
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 USART2EN: USART2 clock enable
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2EN: SPI2 clock enable
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14EN: TIM14 timer clock enable
Bits 7:5 Reserved, must be kept at reset value.
106/742
Set and cleared by software.
0: HDMI CEC clock disabled
1: HDMI CEC clock enabled
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enabled
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Set and cleared by software.
0: TIM14 clock disabled
1: TIM14 clock enabled
Doc ID 018940 Rev 1
RM0091