Table 70. Table; Figure 219. Timeout Intervals For T Low:sext , T Low:mext - STMicroelectronics STM32F05 series Reference Manual

RM0091
.
Table 70.
Symbol
t
TIMEOUT
t
LOW:SEXT
t
LOW:MEXT
1. t
LOW:SEXT
message from the initial START to the STOP. It is possible that, another slave device or the master
will also extend the clock causing the combined clock low extend time to be greater than t
Therefore, this parameter is measured with the slave device as the sole target of a full-speed master.
2. t
LOW:MEXT
of a message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a
slave device or another master will also extend the clock causing the combined clock low time to be
greater than t
device as the sole target of the master.
Figure 219. Timeout intervals for t
SMBCLK
SMBDAT
Bus idle detection
A master can assume that the bus is free if it detects that the clock and data signals have
been high for t
timings)
This timing parameter covers the condition where a master has been dynamically added to
the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.
SMBus timeout specifications
Parameter
Detect clock low timeout
Cumulative clock low extend time (slave
(1)
device)
Cumulative clock low extend time (master
(2)
device)
is the cumulative time a given slave device is allowed to extend the clock cycles in one
is the cumulative time a master device is allowed to extend its clock cycles within each byte
on a given byte. Therefore, this parameter is measured with a full speed slave
LOW:MEXT
Start
t
LOW:MEXT
greater than t
IDLE
HIGH
Doc ID 018940 Rev 1
Inter-integrated circuit (I
, t
LOW:SEXT LOW:MEXT
t
LOW:SEXT
Clk
Ack
t
LOW:MEXT
. (refer to Table 66: I2C-SMBUS specification clock
,
MAX
2
C) interface
Limits
Unit
Min Max
25 35 ms
25 ms
10 ms
LOW:SEXT
Stop
Clk
Ack
t
LOW:MEXT
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