Table 25. Summary Of Dma Requests For Each Channel - STMicroelectronics STM32F05 series Reference Manual

RM0091
Table 25
Table 25. Summary of DMA requests for each channel
Peripherals Channel 1
ADC
SPI
USART
I2C
TIM1
TIM2 TIM2_CH3
TIM3
TIM6 / DAC
TIM15
TIM16
TIM17_CH1
TIM17
TIM17_UP
1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the SYSCFG_CFGR1
register. For more details, please refer to
2. DMA request mapped on this DMA channel only if the corresponding remapping bit is set in the SYSCFG_CFGR1 register.
For more details, please refer to
lists the DMA requests for each channel.
Channel 2
(1)
ADC ADC
SPI1_RX
USART1_TX
I2C1_TX
TIM1_CH1
TIM2_UP
TIM3_CH3
(1)
TIM17_CH1
(1)
TIM17_UP
Section 9.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page
Section 9.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page
Doc ID 018940 Rev 1
Direct memory access controller (DMA)
Channel 3
(2)
SP1_TX
(1)
USART1_RX
I2C1_RX
TIM1_CH2
TIM2_CH2
TIM3_CH4
TIM3_UP
TIM6_UP
DAC
(1)
TIM16_CH1
(1)
TIM16_UP
(2)
(2)
Channel 4
SPI2_RX
(2)
USART1_TX
(1)
USART2_TX
I2C2_TX
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM2_CH4
TIM3_CH1
TIM3_TRIG
(2)
TIM16_CH1
(2)
TIM16_UP
Channel 5
SPI2_TX
(2)
USART1_RX
USART2_RX
I2C2_RX
TIM1_CH3
TIM1_UP
TIM2_CH1
TIM15_CH1
TIM15_UP
TIM15_TRIG
TIM15_COM
135.
135.
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