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Independent watchdog (IWDG)
21.4.2
Prescaler register (IWDG_PR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PR[2:0]: Prescaler divider
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
456/742
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits are write access protected
select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in
order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG_SR
register is reset.
Doc ID 018940 Rev 1
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
seeSection
21.3.3. They are written by software to
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
PR[2:0]
rw
rw
RM0091
16
Res.
0
rw
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