Tsc Registers; Tsc Control Register (Tsc_Cr) - STMicroelectronics STM32F05 series Reference Manual

Touch sensing controller (TSC)
27.6

TSC registers

Refer to
register descriptions.
The peripheral registers can be accessed by words (32-bit).
27.6.1

TSC control register (TSC_CR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
CTPH[3:0]
rw rw rw
15 14 13
SSPSC PGPSC[2:0]
rw rw rw
Bits 31:28 CTPH[3:0]: Charge transfer pulse high
Note: These bits must not be modified when an acquisition is on-going.
Bits 27:24 CTPL[3:0]: Charge transfer pulse low
Note: These bits must not be modified when an acquisition is on-going.
Bits 23:17 SSD[6:0]: Spread spectrum deviation
Note: These bits must not be modified when an acquisition is on-going.
Bit 16 SSE: Spread spectrum enable
Note: This bit must not be modified when an acquisition is on-going.
690/742
Section 1.1 on page 34
28 27 26 25
CTPL[3:0]
rw rw rw rw
12 11 10 9
Res. Res. Res.
rw
These bits are set and cleared by software. They define the duration of the high state of the
charge transfer pulse (charge of C
0000: 1x t
PGCLK
0001: 2x t
PGCLK
...
1111: 16x t
PGCLK
These bits are set and cleared by software. They define the duration of the low state of the
charge transfer pulse (transfer of charge from C
0000: 1x t
PGCLK
0001: 2x t
PGCLK
...
1111: 16x t
PGCLK
These bits are set and cleared by software. They define the spread spectrum deviation which
consists in adding a variable number of period at f
state.
0000000: 1x t
SSCLK
0000001: 2x t
SSCLK
...
1111111: 128x t
SSCLK
This bit is set and cleared by software to enable/disable the spread spectrum feature.
0: Spread spectrum disabled
1: Spread spectrum enabled
Doc ID 018940 Rev 1
of the reference manual for a list of abbreviations used in
24 23 22
rw rw rw
8 7 6
Res. MCV[2:0]
rw rw
).
X
to C
X
SSCLK
21 20 19 18
SSD[6:0]
rw rw rw rw
5 4 3 2
SYNC
IODEF AM
POL
rw rw rw rw
).
S
to the charge transfer pulse high
RM0091
17 16
SSE
rw rw
1 0
START TSCE
rw rw