Figure 277. Operations Required To Receive 0X3478Ae; Figure 278. Lsb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0; Figure 279. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame - STMicroelectronics STM32F05 series Reference Manual

RM0091

Figure 277. Operations required to receive 0x3478AE

Figure 278. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0

When 16-bit data frame extended to 32-bit channel frame is selected during the I
configuration phase, Only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it
corresponds to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in

Figure 279. Example of 16-bit data frame extended to 32-bit channel frame

In transmission mode, when a TXE event occurs, the application has to write the data to be
transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).
The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and
not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun
or overrun conditions.
First read from Data register
conditioned by RXNE=1
0xXX34
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
CK
WS
16-bit data
SD
0 forced
Figure 279
Only one access to the SPIx-DR register
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
Second read from Data register
conditioned by RXNE=1
Transmission
16-bit remaining
MSB
Channel left 32-bit
is required.
0x76A3
0x78AE
MS19597V1
Reception
LSB
Channel right
MS30105V1
MS19598V1
2
S
659/742