Figure 271. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length With Cpol = 0; Figure 272. Msb Justified 24-Bit Frame Length With Cpol = 0; Figure 273. Msb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0 - STMicroelectronics STM32F05 series Reference Manual

RM0091
MSB justified standard
For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.

Figure 271. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0

Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge
(for the receiver).

Figure 272. MSB justified 24-bit frame length with CPOL = 0

Figure 273. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0

CK
Transmission
WS
SD
MSB
CK
Transmission
WS
24 bit data
SD
MSB
CK
Transmission
WS
16-bit data
SD
MSB
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
Reception
16- or 32 bit data
LSB MSB
Channel left
Reception
8-bit remaining
0 forced
LSB
Channel left 32-bit
Reception
16-bit remaining
0 forced
LSB
Channel left 32-bit
Channel right
MS30100 V1
Channel right
MS30101V1
Channel right
MS30102V1
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