Hdmi-Cec Register Map; Table 106. Hdmi-Cec Register Map And Reset Values - STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus
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28.7.7

HDMI-CEC register map

The following table summarizes the HDMI-CEC registers.

Table 106. HDMI-CEC register map and reset values

Offset
Register
CEC_CR
0x00
Reset value
CEC_CFGR
0x04
Reset value
0
CEC_TXDR
0x08
Reset value
CEC_RXDR
0x0C
Reset value
CEC_ISR
0x10
Reset value
CEC_IER
0x14
Reset value
Refer to
OAR[14:0]
0
0
0
0
0
0
0
0
Section 2.2.2 on page 37
Doc ID 018940 Rev 1
0
0
0
0
0
0
0
for the register boundary addresses.
HDMI-CEC controller (HDMI-CEC)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SFT[2:0]
0
0
0
0
0
TXD[7:0]
0
0
0
0
0
RXD[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
717/742

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