Interrupts And Events; Nested Vectored Interrupt Controller (Nvic); Nvic Main Features; Systick Calibration Value Register - STMicroelectronics STM32F05 series Reference Manual

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11

Interrupts and events

11.1

Nested vectored interrupt controller (NVIC)

11.1.1

NVIC main features

● 32 maskable interrupt channels (not including the sixteen Cortex-M0 interrupt lines)
●
4 programmable priority levels (2 bits of interrupt priority are used)
● Low-latency exception and interrupt handling
●
Power management control
● Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to STM32F05xxx Cortex-M0 programming
manual.
11.1.2

SysTick calibration value register

The SysTick calibration value is set to 6000, which gives a reference time base of 1 ms with
the SysTick clock set to 6 MHz (max f
11.1.3

Interrupt and exception vectors

Table 27
Table 27.
-
-3
-2
-1
3
5
6
0
1
2
is the vector table for STM32F05xxx devices.
Vector table
Type of
Acronym
priority
- -
fixed Reset
fixed NMI
fixed HardFault
settable SVCall
settable PendSV
settable SysTick
settable WWDG
settable PVD
settable RTC
Doc ID 018940 Rev 1
/8).
HCLK
Description
Reserved
Reset
Non maskable interrupt. The RCC
Clock Security System (CSS) is
linked to the NMI vector.
All class of fault
System service call via SWI
instruction
Pendable request for system service
System tick timer
Window Watchdog interrupt
PVD through EXTI line detection
interrupt
RTC global interrupt
Interrupts and events
Address
0x0000 0000
0x0000 0004
0x0000 0008
0x0000 000C
0x0000 002C
0x0000 0038
0x0000 003C
0x0000 0040
0x0000 0044
0x0000 0048
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