Timer Synchronization; Debug Mode; Figure 90. Control Circuit In External Clock Mode 2 + Trigger Mode - STMicroelectronics STM32F05 series Reference Manual

Advanced-control timers (TIM1)
2. Configure the channel 1 as follows, to detect rising edges on TI:
–
–
–
–
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.

Figure 90. Control circuit in external clock mode 2 + trigger mode

Counter clock = CK_CNT = CK_PSC
15.3.20

Timer synchronization

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 16.3.15: Timer synchronization on page 323
15.3.21

Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module.
264/742
IC1F=0000: no filter.
The capture prescaler is not used for triggering and does not need to be
configured.
CC1S=01in TIMx_CCMR1 register to select only the input capture source
CC1P=0 and CC1NP='0' in TIMx_CCER register to validate the polarity (and
detect rising edge only).
TI1
CEN/CNT_EN
ETR
Counter register
TIF
Doc ID 018940 Rev 1
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for details.
RM0091
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