Clock Source; Debug Mode; Figure 190. Control Circuit In Normal Mode, Internal Clock Divided By 1 - STMicroelectronics STM32F05 series Reference Manual

Basic timer (TIM6)
19.3.3

Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 190
without prescaler.

Figure 190. Control circuit in normal mode, internal clock divided by 1

Counter clock = CK_CNT = CK_PSC
19.3.4

Debug mode

When the microcontroller enters the debug mode (Cortex™-M0 core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. .
446/742
shows the behavior of the control circuit and the upcounter in normal mode,
CK_INT
CEN=CNT_EN
UG
CNT_INIT
Counter register
Doc ID 018940 Rev 1
31 32 33 34 35 36 00 01 02 03 04 05 06 07
RM0091