Clock Configuration Register (Rcc_Cfgr) - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
7.4.2

Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
31 30 29
Res Res Res Res
15 14 13
ADCP
Res Res Res
RE
rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:24 MCO: Microcontroller clock output
Note: This clock output may have some truncated cycles at startup or during MCO clock
Bits 23:22
94/742
28 27 26 25
Res MCO[2:0]
rw rw
12 11 10 9
Res PPRE[2:0]
rw rw
Set and cleared by software.
000: MCO output disabled, no clock on MCO
001: Reserved
010: Reserved
011: HSI14 clock selected
100: System clock (SYSCLK) selected
101: HSI clock selected
110: HSE clock selected
111: PLL clock divided by 2 selected
source switching.
Reserved, must be kept at reset value.
Doc ID 018940 Rev 1
24 23 22 21
Res Res
rw rw
8 7 6 5
HPRE[3:0]
rw rw rw rw
20 19 18 17
PLL
PLLMUL[3:0]
XTPRE
rw rw rw rw
4 3 2 1
SWS[1:0]
rw r r rw
RM0091
16
PLL
SRC
rw
0
SW[1:0]
rw