I2C1 Block Diagram; Figure 195. I2C1 Block Diagram - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I
23.4.1

I2C1 block diagram

The block diagram of the I
2
Figure 195. I C1 block diagram
SYSCLK
I2CCLK
HSI
RCC_I2C1SW
(from reset and
clock
controller)
PCLK
The I2C1 is clocked by an independent clock source which allows to the I2C to operate
independently from the PCLK frequency.
This independent clock source can be selected for either of the following two clock sources:
●
HSI: high speed internal oscillator (default value)
●
SYSCLK: system clock
Refer to Reset and clock control (RCC) section for more details.
I2C1I/Os support 20 mA output current drive for Fast Mode Plus operation. This is enabled
by setting the driving capability control bits for SCL and SDA in the SYSCFG configuration
register 1 (SYSCFG_CFGR1) section.
470/742
2
C) interface
2
C1 interface is shown in
Data control
Shift register
WUPEN
SMBUS
generation/
Wakeup
on
address
Clock control
match
Master clock
generation
Slave clock
stretching
SMBus Alert
control &
Registers
APB bus
Doc ID 018940 Rev 1
Figure
Digital
noise
filter
PEC
check
Digital
noise
filter
SMBus
Timeout
check
status
195.
From system configuration
controller (SYSCFG)
FM+ drive
Analog
noise
GPIO
I2C1_SDA
filter
logic
From system configuration
controller (SYSCFG)
FM+ drive
Analog
noise
GPIO
I2C1_SCL
filter
logic
I2C1_SMBA
RM0091
MS19873V2