Dma Channel X Configuration Register (Dma_Ccrx) (X = 1 - STMicroelectronics STM32F05 series Reference Manual

Direct memory access controller (DMA)
10.4.3

DMA channel x configuration register (DMA_CCRx) (x = 1..5,

where x = channel number)
Address offset: 0x08 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
MEM2
Res. PL[1:0]
MEM
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Bits 31:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory to memory mode
This bit is set and cleared by software.
0: Memory to memory mode disabled
1: Memory to memory mode enabled
Bits 13:12 PL[1:0]: Channel priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
Bits 11:10 MSIZE[1:0]: Memory size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bits 9:8 PSIZE[1:0]: Peripheral size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bit 7 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory increment mode disabled
1: Memory increment mode enabled
Bit 6 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral increment mode disabled
1: Peripheral increment mode enabled
Bit 5 CIRC: Circular mode
This bit is set and cleared by software.
0: Circular mode disabled
1: Circular mode enabled
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27 26 25 24
Res. Res. Res. Res.
11 10 9 8
MSIZE[1:0] PSIZE[1:0]
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Doc ID 018940 Rev 1
23 22 21 20
Res. Res. Res. Res.
7 6 5
MINC PINC CIRC DIR
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19 18 17
Res. Res. Res.
4 3 2 1
TEIE HTIE TCIE
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RM0091
16
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0
EN
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